FIG. 1 is a circuit diagram showing a drive circuit of a display. The drive circuit includes eight source drivers 103A˜103H connected to source lines 113, and four gate drivers 106 connected to the gate lines 116. The source lines 113 and gate lines 116 are formed in an LCD panel 105, and pixels having a TFT (not shown) as a switching device are arranged at the intersections thereof.
Clock signals or the like are transmitted in parallel to the gate drivers 106 from the control circuit 101, and clock signals, digital image data signals, latch signals and others are transmitted to the source drivers 103A˜103H from the control circuit 101 to control each of the source drivers.
On the other hand, a start pulse signal (SP) is transmitted to only the first source driver 103A at the first stage. After the first source driver 103A receives the image data, the start pulse signal is transferred to the second source driver 103B at the next stage from the first source driver 103A. Then, the second source driver 103B operates in the same manner as that of the first source driver 103A. Thus, as shown by the arrows in FIG. 1, the start pulse signal is transferred from first source driver 103A to the eighth source driver 103H.
FIG. 2 is a timing chart showing signals inputted into the source drivers in the circuit of the display unit having source drivers that are cascade-connected to each other as shown in FIG. 1. Clock signal (CLK) and digital image data signals (D00 to Dxx) are inputted into the source drivers 103A˜103H. The start pulse signal (SP) illustrated in the timing chart is inputted into the first source driver 103A at the first stage. The first source driver 103A starts to receive the digital image data two clocks after the falling edge of the start pulse. After the first source driver 103A receives the digital image data from the control circuit 101, the first source driver 103A provides a start pulse signal (P103A to 103B) to enable the second source driver 103B.
In a traditional RSDS interface, the start pulse signal is a TTL signal. The impedance of the printed circuit board in which the start pulse signal line is built retards the transmission of the start pulse signal (SP) from the control circuit to the source drivers, which results in a longer time for the start pulse signal (SP) to be transferred to the source drivers. Therefore, the start of the source drivers and the receiving of the digital image data signals may be asynchronous. Moreover, when the frequency of the clock signal is increased, the source driver will start to receive the image data more clocks after the falling edge of the start pulse since the clock period is decreased.
Therefore, a new structure that may resolve the foregoing problem is required.